1. Field of the Invention
The present invention relates to a resistive random access memory (RRAM) and method for manufacturing the same and, in particular, to a PRAM with a metal-insulator-metal (MIM) structure, using stacked dielectrics of semiconductor-oxide/nano-crystal (nc) metal-oxide/metal-oxynitride, and different work-function top and bottom electrodes. The RRAM device is implemented in stacked dielectrics of GeOx/nc-TiO2/TaON with low cost top (Ni) and bottom (TaN) electrodes. This RRAM device has special merits of ultra-low sub-100 fJ switching energy, tight distributions of set/reset currents and extremely long endurance of 5×109 cycles simultaneously.
2. Description of the Prior Art
According to International Technology Roadmap for Semiconductors (ITRS) at www.itrs.net, Flash Non-Volatile Memory (NVM) will continue to scale down into sub-20 nm, by replacing the current poly-Si Floating-Gate (FG) with SiN Charge Trapping (CT) structure. However, the degraded endurance from 105 to 104 program/erase cycles is a fundamental physics limitation due to the smaller amount of charges stored in the sub-20 nm cell size. Such degraded endurance is unsuitable for high-end products such as solid-state drive (SSD), and therefore new NVM devices should be developed. To address this issue, non-charge-based resistive random access memory (RRAM) has attracted much attention, and the simple cross-point structure is more suitable for embedded NVM applications and low-cost three-dimensional (3D) integration. However, high set/reset currents, high forming power, wide set/reset margin and poor endurance are difficult challenges for RRAM.